1. Field of the Invention
This invention relates generally to Dynamic Random Access Memory structures and systems, and particularly, to an embedded DRAM (eDRAM) micro-cell array architecture including a micro-cell redundancy scheme.
2. Discussion of the Prior Art
Embedded DRAMs with wide data bandwidth and wide internal bus width have been proposed for L2 (level-2) cache to replace conventional SRAM cache. Since each DRAM memory cell is formed by one transistor and a capacitor, the physical size of DRAM cache is significantly smaller than that of six-transistor SRAM for same density. In order to meet performance requirements, DRAMs for L2 cache are made of a plurality of blocks (here called micro-cells). A block is a small DRAM array unit formed by a plurality of wordlines (typically from 64 to 128) and a plurality of bitline pairs (typically from 64 to 128). The size of a micro-cell is much smaller (e.g., 16X to 256X) than a block of a conventional stand-alone DRAM. Normally, only one micro-cell of a bank of an eDRAM is activated. Sometimes, micro-cells from different banks can be accessed simultaneously. The read and write speed of such eDRAMs can be quite fast due to very light wordline and bitline loading.
In order to effectively utilize the large DRAM cache size for cache, a small SRAM array about the same size of an eDRAM micro-cell is used. The SRAM is served as the cache interface that is placed in between eDRAM and the requesting processor(s). A wide internal bus (64 to 1024) is provided for data transferring among eDRAM, SRAM and the processor(s). To be more specific, data residing in the cells of a wordline of a micro-cell of eDRAM are read and amplified in a group of primary sense amplifiers before being sent to corresponding secondary sense amplifiers. These data are then sent to the SRAM and stored in the cells at the same wordline location. At the same time, the TAG memory records the micro-cell address of which the data are in the cache. The data are finally transferred to the requesting processor(s). Normally, neither column address nor column decoding is necessary for the wide bandwidth eDRAM configuration.
One challenge of the wide bandwidth design is that it is difficult to provide an effective row and column redundancy scheme to fix any defective elements. This is especially difficult for the column redundancy since most of the existing approaches requires a column address to indicate failed column elements for repair. In a conventional DRAM array, bitline pairs are grouped hierarchically by the column address. Each time, only one data from a group of the bitline pairs is selected to be transferred out via the local and global datalines. Therefore, the most common redundancy approach for the conventional DRAM is to provide repair for a whole group of bitlines using the provided column address. However, for a wide bandwidth eDRAM, data from every pair of bitlines must all be sent out. Alternately, all the data lines from eDRAM are simultaneously fed to SRAM, and all the datalines from SRAM are then fed to the processor(s). For such a one-to-one direct wiring, if any of them fail and no redundancy is offered, the chip must be discarded. If redundancy bitlines are provided, it is not easy to correctly replace the failed bitlines and reroute them so the data would still be kept in right order. It is especially hard when there is no column address available.
It would be highly desirable to provide a micro-cell redundancy scheme for repairing defected memory arrays of a wide data bandwidth embedded DRAM.
It would be further highly desirable to provide a micro-cell array eDRAM architecture that includes a micro-cell redundancy replacement scheme wherein a micro-cell array itself is utilized as the unit for redundancy replacement. That is, if any eDRAM wordline, bitline or cell is found defective, then the whole micro-cell would be replaced.
It is an object of the present invention to provide a micro-cell redundancy scheme for repairing defected memory arrays of a wide data bandwidth embedded DRAM.
It is another object of the present invention to provide a micro-cell array eDRAM architecture that includes a micro-cell redundancy replacement scheme wherein a micro-cell array itself is utilized as the unit for redundancy replacement.
Another object of the present invention is to provide micro-cell redundancy architectures for flexible and reliable eDRAM array repairing.
It is a further object of the present invention to provide a system and method for effectively testing the micro-cell redundancy elements.
According to the principles of the invention, there is provided for an embedded semiconductor dynamic random access memory (eDRAM) memory architecture comprising one or more banks of micro-cell arrays with each micro-cell comprising a plurality of DRAM memory elements for storing data, a micro-cell array redundancy system comprising: a plurality of redundant micro-cell arrays, one or more of the plurality of redundant micro-cells associated with a micro-cell array bank; a mechanism for mapping eDRAM micro-cell arrays previously determined as being defective with a corresponding good redundant micro-cell array implemented as a replacement array for storing data; and a logic circuit for facilitating data read and write operations, the logic circuit implementing the mapping mechanism for enabling read and write access to a replacement redundant micro-cell array associated with a micro-cell array determined as defective.
The micro-cell redundancy system may be implemented for an embedded DRAM cache having a SRAM cache interface. For each memory array bank, at least one micro-cell is prepared as the redundancy to replace a defected micro-cell within the bank. After array testing, any defective micro-cell inside a bank is replaced with a redundancy micro-cell for that bank. A look-up table is established and implemented, for example, by a fuse bank, where each redundant micro-cell address versus its corresponding repaired micro-cell address is recorded. Two embodiments of micro-cell redundancy are proposed, with a preferred embodiment limiting redundant micro-cells to only replace the defective micro-cells within the same bank in order to allow simultaneous multi-bank operation. When reading data from eDRAM, or writing data to eDRAM, the micro-cell array address must be checked to determine whether that is the original micro-cell, or the redundant micro-cell.
The micro-cell redundancy scheme of the invention provides a flexible and reliable method for high-performance, wide bandwidth eDRAM applications.